Method of fabricating a dual damascene structure in an integrate

Details Method of fabricating a dual damascene structure in an integrate Method of fabricating a dual damascene structure in an integrate

1999-03-23

2000-12-05

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438638, 438666, 438669, 438672, 438687, H01L 214763

Patent

active

06156642&

ABSTRACT:
A semiconductor fabrication method is provided for fabricating a dual damascene structure in a semiconductor device. By this method, a dielectric layer is first formed over a semiconductor substrate, and then a void structure including a via hole and a trench is formed in the dielectric layer. Next, a metallization structure is formed in the void structure in the dielectric layer, and after this, a special etching agent is used to treat the exposed surface of the metallization structure so as to make the exposed surface substantially rugged. Finally, a passivation layer is formed over the metallization structure, with the metallization structure serving as the intended dual damascene structure. The roughness of the exposed surface of the metallization structure can help buffer the stresses from the deposition of the passivation layer thereon and also help strengthen the adhesion between the passivation layer and the metallization structure, so that the passivation layer can be firmly secured to the metallization structure. As a result, the passivation layer cannot peel off the metallization structure, and thereby can more reliably help prevent the metallization structure from oxidizing and the atoms/ions in the metallization structure from diffusing into the subsequently formed dielectric layer above the metallization structure. The resultant IC device is therefore more reliable to use.

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