Semiconductor device having variable impurity concentration poly

Details Semiconductor device having variable impurity concentration poly Semiconductor device having variable impurity concentration poly

1991-07-12

1993-10-26

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257383, 257384, 257385, 257413, 257755, 257756, 257757, 257770, 437191, 437192, 437200, H01L 2904, H01L 2144

Patent

active

052568946

ABSTRACT:
The present invention relates to a semiconductor device used as a gate electrode or interconnection, in which a polysilicon layer in a laminate comprising a polysilicon layer doped with an impurity and a refractory metal silicide layer has an impurity concentration that is reduced close to a boundary between the polysilicon layer and the refractory metal silicide layer. With this structure, the difference in oxidation speed between the polysilicon layer and the silicide layer is smaller in comparison with a conventional structure, and thus peeling due to bird's beaks can be prevented. The semiconductor device of this structure can be realized by a two-layer polysilicon structure in which the upper layer in contact with the refractory metal silicide layer has a lower impurity concentration, or by a structure in which the peak of the impurity concentration profile is set to be deep within the polysilicon layer during ion implantation.

REFERENCES:
patent: 4584760 (1986-04-01), Okazawa
patent: 4755865 (1988-07-01), Wilson
patent: 4945070 (1990-07-01), Hsu
Patent Abstracts of Japan, vol. 13, No. 74 (E-717) Feb. 20, 1989, & JP-A-63 255 964 (Toshiba Corp.) Oct. 24, 1988.
V. L. Rideout, IBM Technical Disclosure Bulletin, "Fabrication Low Resistance Intercooection Lines and Fet Gates in a Single Step", vol. 21, No. 3, Aug. 1978, pp. 1250-1251.
Dan Peters, IEEE Transactions on Electron Devices, "Implanted-Silicided Polysilicon Gates for VLSI Transistors", vol. ED-33, No. 9, Sep. 1986, pp. 1391-1393.

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