Method and apparatus using silicide layer for protecting integra

Details Method and apparatus using silicide layer for protecting integra Method and apparatus using silicide layer for protecting integra

1999-04-23

2000-09-12

Picardat, Kevin M.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438570, 438584, 438597, 438655, H01L 214763

Patent

active

061177628

ABSTRACT:
A method and apparatus for protecting semiconductor integrated circuits from reverse engineering. Semiconductor active areas are formed on a substrate. A silicide layer is formed both over at least one active area of the semiconductor active areas and over a selected substrate area for interconnecting the at least one active area with another area through the silicide area formed on the selected substrate area. In a preferred embodiment a silicide layer formed on a first active area is interconnectingly merged laterally with a silicide layer formed on a second active area through the silicide layer formed on the selected substrate area.

REFERENCES:
patent: 4139864 (1979-02-01), Schulman
patent: 4267578 (1981-05-01), Vetter
patent: 4583011 (1986-04-01), Pechar
patent: 5571735 (1996-11-01), Mogami et al.
patent: 5783846 (1998-07-01), Baukus et al.
"Silicides for Gates and Interconnections," VLSI Technology, edited by S.M. Sze, Bell Laboratories, Inc., pp. 372-380 (1983).
Thomas Frederickson, "A Multiple-Layer-Metal CMOS Process," Intuitive CMOS Electronics, Section 5.6., pp. 134-146 (1989).

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