Integrated circuit that supports and method for wafer-level test

Details Integrated circuit that supports and method for wafer-level test Integrated circuit that supports and method for wafer-level test

1996-09-17

1998-09-15

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

36518905, 36523008, G11C 1300

Patent

active

058089470

ABSTRACT:
An integrated circuit is formed on a die that is formed as a detachable part of a semiconductor wafer. The wafer includes both a wafer test-mode path that is operable to carry a wafer test-mode signal and a wafer power-supply path that is operable to carry a wafer power-supply signal. The integrated circuit includes functional circuitry that supports normal and wafer-test modes of operation and that is coupled to the wafer test-mode path before the die is detached from the wafer. The functional circuitry is operable to function in the wafer test mode of operation when the wafer test-mode signal has a first state. The integrated circuit also includes a wafer test-mode power circuit that is coupled to the functional circuitry, and that is coupled to the wafer power-supply path and the wafer test-mode path before the die is detached from the wafer. The power circuit is operable to couple the wafer power-supply path to the functional circuitry when the wafer test-mode signal has the first state. When the wafer test-mode signal has a second state, the wafer test-mode power circuit is operable to uncouple the wafer power-supply path from the functional circuitry, and the functional circuitry is operable to function in the normal mode of operation.

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"Wafer Burn-In Isolation Circuit," IBM Technical Disclosure Bulletin, 32(6B):442-443, Nov. 1989.
Bove et al., "Impedance Terminator For AC Testing Monolithic Chips," IBM Technical Disclosure Bulletin, 15(9):2681-2682, Feb. 1973.
"Wafer Level Test and Burn-In," IBM Technical Disclosure Bulletin, 33(8):1-2, Jan. 1991.

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