Memory system having flexible bus structure and method

Details Memory system having flexible bus structure and method Memory system having flexible bus structure and method

1997-04-23

2000-02-01

Robertson, David L.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

711154, 36523003, 36523006, G06F 1206

Patent

active

060214597

ABSTRACT:
A memory system having a memory controller connected to multiple memory devices by way of a system bus. The memory controller issues device select, memory program and memory read instructions for the memory devices over the system bus, with the device select instructions including a device select address and a device select command. The memory devices each include an array of memory cells and a memory operation manager which functions to carry out memory read and program operations on the array. The memory operation manager includes an address comparator which compares the device select address received on the system bus with a local address stored in the memory device and a command decoder which detects commands on the system bus, with the memory operation manager operating to switch the memory device from a device-disabled state to a device-enabled state when the memory device receive a select address which matches the local address together with one of the device select commands.

REFERENCES:
patent: 5568647 (1996-10-01), Kobayashi

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