Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1997-08-19
1999-09-21
Robertson, David L.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
395381, G06F 1200
Patent
active
059567538
ABSTRACT:
The method and apparatus are employed within a microprocessor capable of generating speculative memory accesses instructions. Certain instructions access memory locations containing speculatable information while others access memory locations containing non-speculatable information. Memory-type values indicating the speculatability or non-speculatability of memory locations are stored within a translation lookaside buffer. Prior to executing a speculative memory instruction, the microprocessor accesses the translation lookaside buffer to determine whether the memory location targeted by a memory instruction contains speculatable or non-speculatable information. Then, depending upon the memory-type value found in the translation lookaside buffer, execution of the speculative memory instruction is performed immediately or is deferred until the instruction is no longer speculative. In protected mode, the translation lookaside buffer caches linear addresses, physical addresses and corresponding memory-type values. In real mode, the translation lookaside buffer caches the memory-type values along with physical addresses, but does not cache linear addresses. The translation lookaside buffer is operated in both protected mode and real mode to access the cached memory-type information.
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Akkary Haitham
Glew Andrew F.
Intel Corporation
Robertson David L.
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