Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Patent
1995-03-13
1996-03-26
Thomas, Laura
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
174260, 174261, 174262, 361790, 361789, 361783, 361784, 257666, 439 65, 439 69, 439 74, H05K 100
Patent
active
055022898
ABSTRACT:
A circuit assembly which includes a semiconductor die having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on the first surface. A first element having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on one of its surfaces is mounted on and at least partially supported at its second surface by the first surface of the semiconductor die. The first element is positioned such that the semiconductor die electrical contact is exposed. A fine wire conductor having first and second ends is connected at its first end to either the semiconductor die electrical contact or the first element electrical contact. A method of manufacturing this circuit assembly is also disclosed.
REFERENCES:
patent: 4296456 (1981-10-01), Reid
patent: 4320438 (1982-03-01), Ibrahim et al.
patent: 4714952 (1987-12-01), Takekawa et al.
patent: 5012323 (1991-04-01), Farnworth
patent: 5294826 (1994-05-01), Marcantonio et al.
"Matsushita's Stacked Chip Module," Semiconductor Packaging Update, vol. 4, No. 5, pp. 9, 1989.
Stuart N. Shanken and John C. Carson, "Very High Density 3-D Packaging of Integrated Circuits," ISHM 1989 Proceedings, Baltimore, Maryland, pp. 1-7.
Takaashi Oksaki, "Electronic Packaging in the 90s--A Perspective from Asia," IEEE, 40th Electron, Components and Technology Conference, vol. 1, May 20-23, Las Vegas, NV, 1990, pp. 1-8.
Rao R. Tummala, "Electronic Packaging in the 90s--A Perspective from America," IEEE, 40th Electron, Components and Technology Conference, vol. 1, May 20-23, Las Vegas, NV, 1990, pp. 9-15.
H. Wessely et al., "Electronic Packaging in the 90s--A Perspective from Europe," IEEE, 40th Electron, Components and Technology Conference, vol. 1, May 20-23, Las Vegas, NV, pp. 16-33.
John C. Carson and Stuart N. Shanken, "High Volume Producibility and Manufacturing of Z-Plane Technology," SPIE, Material, Devices, Techniques and Applications for Z-Plane Focal Plane Array, (FPA) Technology, vol. 1097, 1989, pp. 138-149.
Myles F. Suer and John C. Carson, "Future Capabilities of Z-Plane Technology," SPIE, Materials, Devices, Techniques, and Applications for Z-Plane Focal Plane Array (FPA) Technology, vol. 1097, 1989, pp. 41-49.
Lin Peng-Cheng
Takiar Hem P.
National Semiconductor Corporation
Thomas Laura
LandOfFree
Stacked multi-chip modules and method of manufacturing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Stacked multi-chip modules and method of manufacturing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked multi-chip modules and method of manufacturing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-917544