Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1997-09-11
1999-07-06
Hardy, David B.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
H01L 27112
Patent
active
059200995
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
Memories into which data are permanently written are required for many electronic systems. Such memories are referred to, inter alia, as read-only memories.
For very large quantities of data plastic discs coated with aluminum are often used as read-only memories. In the coating these plastic discs have two kinds of dot-like depressions which are assigned to the logic values zero and one. The information is stored digitally in the arrangement of these depressions. Such discs are referred to as compact discs and are widespread for the digital storage of music.
A reading device in which the disc is mechanically rotated is used to read the data stored on a compact disc. The dot-like depressions are scanned by means of a laser diode and a photo cell. Typical scanning rates in this context are 2.times.40 kHz. Five Gbits of information can be stored on a compact disc.
The reading device has moving parts which are subject to mechanical wear, require a comparatively large volume and only permit slow data access. Moreover, the reading device is sensitive to jolts and can therefore only be used to a limited degree in mobile systems.
Read-only memories on a semiconductor basis are known for the storage of relatively small quantities of data. Such read-only memories are often realized as a planar integrated silicon circuit in which MOS transistors are used. The MOS transistors are respectively selected via the gate electrode which is connected to the word line. The input of the MOS transistor is connected to a reference line and the output to a bit line. During the reading process it is evaluated whether a current is flowing through the transistor or not. The stored information is assigned correspondingly. The storage of information is usually brought about technically in that the MOS transistors have different threshold voltages as a result of different implantations in the channel region.
These memories on a semiconductor basis permit random access to the stored information. The electric power which is necessary for reading the information is considerably smaller than in a reading device with a mechanical drive. Since no mechanical drive is necessary to read the information, the mechanical wear and the sensitivity to jolts are eliminated. Read-only memories on a semiconductor basis can therefore also be used for mobile systems.
The silicon memories described have a planar structure. Thus, a minimum area of approximately 6 to 8 F.sup.2 is required per memory cell, F being the smallest size of structure which can be manufactured with the respective technology. With 1 .mu.m technology, planar silicon memories are therefore limited to storage densities of approximately 0.14 bits per .mu.m.sup.2.
It is known to increase the storage density in planar silicon memories by arranging the MOS transistors in rows. In each row the MOS transistors are connected in series. The MOS transistors are read out by driving on a row-by-row basis in the manner of an "NAND" architecture. For this only two connections are required per row, between which connections the MOS transistors which are arranged in the row are connected in series. Source/drain regions, which are connected to one another, of adjacent MOS transistors can then be realized as a continuous doped region. As a result, the area required per memory cell can be reduced to theoretically 4 F.sup.2 (F: the smallest size of structure which can be manufactured with the respective technology). Such a memory cell array is known for example from H. Kawagoe and N. Tsuji in IEEE J. Solid-State Circuits, vol. SC-11, p. 360, 1976.
SUMMARY OF THE INVENTION
The invention is based on the problem of disclosing a read-only memory cell array on a semiconductor basis in which an increased storage density is achieved and which can be manufactured with few manufacturing steps and a high yield. Furthermore, a process for manufacturing such a memory cell array is to be disclosed.
In general terms the present invention is a read-only memory cell array. A plurality of in
REFERENCES:
patent: 5306941 (1994-04-01), Yoshida
Patent Abstract of Japan, (E-1299, Dec. 18, 1992, vol. 16, No. 579) JP 4-226071 (A), Aug. 14, 1992, Semiconductor Memory Device, (Patent attached, pp. 701-708).
Patent Abstract of Japan, (E-1421, Aug. 25, 1993, vol. 17,, No. 466) JP 5-110036 (A), Apr. 30, 1993, Semiconductor Memory and Manufacture Thereof, (Patent attached, pp. 223-227).
IEEE Journal of Solid-State Circuits, vol. SC-11, No. 3, Jun. 1976, Minimum Size ROM Structure Compatible with Silicon-Gate E/D MOS LSI, H. Kawagoe et al, pp. 360-364.
Hofmann Franz
Krautschneider Wolfgang
Risch Lothar
Hardy David B.
Siemens Aktiengesellschaft
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