Semiconductor memory device with delayed precharge signals

Details Semiconductor memory device with delayed precharge signals Semiconductor memory device with delayed precharge signals

1985-05-20

1989-03-14

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Signals

365203, 365227, 365233, G11C 700

Patent

active

048130214

ABSTRACT:
A semiconductor memory device includes memory cells arranged in a matrix array, a plurality of pairs of bit lines, each pair of bit lines being connected to the memory cells on the same column, a plurality of pairs of switching MOS transistors, each pair of MOS transistors being connected between a power source terminal and each pair of bit lines, and a precharge control circuit for supplying a control signal to the gates of the switching MOS transistors. This memory device further includes delay circuits connected in series with each other, and the delay circuits delay the control signal from the precharge control circuit and supply the control signal to the gates of the switching MOS transistors at different timings.

REFERENCES:
patent: 3848237 (1974-11-01), Geilhufe
patent: 3953839 (1976-04-01), Dennison et al.
patent: 4123799 (1978-10-01), Peterson
patent: 4204277 (1980-05-01), Kinoshita
patent: 4222112 (1980-09-01), Clemons et al.
patent: 4223396 (1980-09-01), Kinoshita
patent: 4379344 (1983-04-01), Ozawa et al.

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