Programmable semiconductor read only memory device

Static information storage and retrieval – Systems using particular element – Capacitors

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Details

365230, G11C 1124

Patent

active

047824662

ABSTRACT:
A programmable semiconductor read only memory device which includes a memory cell array formed by a plurality of memory cells arranged in a matrix arrangement. Each memory cell in the memory cell array includes a transistor having a gate thereof coupled to a word line, and a capacitor having an insulator layer, having a first terminal coupled to a bit line and having a second terminal coupled to the transistor so that the capacitor is grounded via the transistor. The insulator layer of the capacitor of a selected memory cell breaks down when a specific word line and a specific bit line coupled to the selected memory cell are driven, thereby making the capacitor conductive.

REFERENCES:
patent: 4272832 (1981-06-01), Ito
patent: 4520466 (1985-05-01), Mashiko

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