Method for performing in-line bank conflict detection and resolu

Details Method for performing in-line bank conflict detection and resolu Method for performing in-line bank conflict detection and resolu

1997-06-25

1999-07-27

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711105, 711141, 711133, 711127, G06F 1200

Patent

active

059308192

ABSTRACT:
A data cache unit associated with a processor, the data cache unit including a multi-ported non-blocking cache receiving a data access request from a lower level device in the processor. A memory scheduling window includes at least one row of entries, wherein each entry includes an address field holding an address of the access request. A conflict map field within at least some of the entries is coupled to a conflict checking unit. The conflict checking unit responds to the address fields by setting bits in the conflict map fields to indicate intra-row conflicts between entries. A picker coupled to the memory scheduling window responds to the conflict map fields so as to identify groups of non-conflicting entries to launch in parallel at the multi-ported non-blocking cache.

REFERENCES:
patent: 5274790 (1993-12-01), Suzuki
patent: 5623628 (1997-04-01), Brayton et al.
patent: 5761714 (1996-04-01), Liu et al.
patent: 5781924 (1997-03-01), Zaitzeva et al.
patent: 5787267 (1995-06-01), Leung et al.

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