Transaction checking system for verifying bus bridges in multi-m

Details Transaction checking system for verifying bus bridges in multi-m Transaction checking system for verifying bus bridges in multi-m

1997-07-31

1999-07-27

Ray, Gopal C.

395555, 395309, G06F 1300

Patent

active

059304820

ABSTRACT:
A transaction checking system and method to verify bus bridges in multi-master bus systems are described. A state machine model is created for each bus in the system. An initiator cycle list and a target cycle list store corresponding bus cycle state machine objects and transition their states according to bus signals. The bus cycle state machines provide a mechanism of persistent storage for other verification tasks. A bus bridge model may store a copy of each configuration register for the bus bridge, thereby monitoring current state of the bus bridge. False failures due to data merging, data collapsing and address remapping are avoided. A cache model and a cycle-based messaging system provide verification of proper cache master operation. Cache coherency errors may also be detected. A statistics keeping object may be created to monitor and store all pertinent performance information for the bus bridge. The transaction checking system may monitor the state of the bus bridge in a device independent manner and with tighter verification. The cycle-based approach to verification of internal states of a bus bridge results in a sound resolution of bus cycles with a better predictability of possible failures.

REFERENCES:
patent: 5634073 (1997-05-01), Collins et al.
patent: 5649161 (1997-07-01), Andrade et al.
patent: 5774681 (1998-06-01), Kunishige
patent: 5813038 (1998-09-01), Thome et al.

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