Semiconductor memory device

Static information storage and retrieval – Addressing – Plural blocks or banks

Patent

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Details

Other Related Categories

36523008, G11C 1300

Type

Patent

Status

active

Patent number

059301953

Description

ABSTRACT:
A semiconductor memory device includes a plurality of main bit lines; a first bank having a plurality of memory cells, a plurality of word lines and a plurality of sub-bit lines; a second bank having a plurality of memory cells, a plurality of word lines and a plurality of sub-bit lines; an auxiliary conductive region connected to one of the plurality of main bit lines, the auxiliary conductive region being shared by the first bank and the second bank; a first bank selection transistor for selectively connecting one of the plurality of sub-bit lines of the first bank to the auxiliary conductive region; a second bank selection transistor for selectively connecting one of the plurality of sub-bit lines of the second bank to the auxiliary conductive region; and a first bank selection line shared by the first bank selection transistor and the second bank selection transistor.

REFERENCES:
patent: 5499216 (1996-03-01), Yamamoto

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