Semiconductor memory device having two P-well layout structure

Details Semiconductor memory device having two P-well layout structure Semiconductor memory device having two P-well layout structure

1997-12-18

1999-07-27

Nelms, David

Static information storage and retrieval

Systems using particular element

Flip-flop

257903, G11C 1100

Patent

active

059301635

ABSTRACT:
This invention relates to P- and N-well regions where inverters constituting an SRAM cell are formed. The P-well region is divided into two parts, which are laid out on the two sides of the N-well region. Boundaries (BL11, BL12) are formed to run parallel to bit lines (BL, /BL). With this layout, diffusion layers (ND1, ND2) within the P-well regions can be formed into simple shapes free from any bent portion, reducing the cell area.

REFERENCES:
patent: 5754468 (1998-05-01), Hobson

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