CMOS semiconductor device having dual-gate electrode constructio

Details CMOS semiconductor device having dual-gate electrode constructio CMOS semiconductor device having dual-gate electrode constructio

1997-01-24

1998-11-17

Dutton, Brian

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438655, H01L 213205, H01L 214763

Patent

active

058376011

ABSTRACT:
A semiconductor device in which mutual diffusion of doped impurities occurring through an upper silicide electrode layer is prevented. A silicide electrode layer is doped with both the same degree of p-type impurities as the concentration of p-type impurities of the lower gate electrode layer and the same degree of n-type impurities as the concentration of n-type impurities. As a result, the concentration of doped impurities of the gate electrode layer is balanced at the two sides of the interface of the pMOS side and nMOS side. Therefore, heat diffusion caused by subsequent heat treatment is prevented and the problem of mutual diffusion can be solved. The present invention is also suitable for the SALICIDE process. Even when the silicide electrode layer is formed simultaneously on an extremely shallow source or drain regions since the concentration of the impurities of the silicide electrode layer was initially high, the lower impurities will not be drained so the contact resistance will not be made to deteriorate. As a result, it becomes easy for the SALICIDE process to be applied to submicron devices. In the method of production of the present invention, the silicide electrode layer is formed by the CVD method or the sputtering method and the impurities doped during this process, so no special step has to be provided for introducing the impurities.

REFERENCES:
patent: 4786611 (1988-11-01), Pfiester
patent: 5341014 (1994-08-01), Fujii et al.
patent: 5355010 (1994-10-01), Fujii et al.
patent: 5633523 (1997-05-01), Kato

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