PLL circuit with pseudo-synchronization control device

Details PLL circuit with pseudo-synchronization control device PLL circuit with pseudo-synchronization control device

1998-01-28

1999-07-27

Kinkead, Arnold

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 18, 331 25, 327156, 327159, 375376, 348536, H03L 700, H03L 708

Patent

active

059297115

ABSTRACT:
A PLL circuit includes a phase comparator that compares an external synchronizing signal and an internal synchronizing signal to detect a phase difference therebetween, and a voltage-controlled oscillator that generates the internal synchronizing signal by oscillation thereof. The frequency of the voltage-controlled oscillator is controlled depending upon the phase difference, so that the internal synchronizing signal becomes in phase with the external synchronizing signal. A limiting device is provided, which limits the phase of the external synchronizing signal supplied to the phase comparator to be within a predetermined window period that includes the timing of generation of the internal synchronizing signal.

REFERENCES:
patent: 5457428 (1995-10-01), Alder et al.
patent: 5663688 (1997-09-01), Delmas et al.

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