High speed modular internal microprocessor bus system

Details High speed modular internal microprocessor bus system High speed modular internal microprocessor bus system

1997-12-31

1999-12-14

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710107, 710129, G06F 1340, G06F 1338, G06F 13364

Patent

active

060031042

ABSTRACT:
A CPU of a microprocessor includes a common bus, a bus interface unit (BIU), and a plurality of module units. The BIU has a plurality of first ports coupled to respective first ports of the module units via dedicated buses therebetween and has a second port coupled to a first port of the common bus. The module units each include a second port coupled to respective second ports of the common bus. Communication between the module units is routed through and controlled by the BIU. To request a transaction, a module unit (the initiator) sends a request to the BIU via its dedicated bus to the BIU. The BIU arbitrates among present requests and, in response thereto, grants the arbitration winner's request and transmits a command to the target of the requested transaction. Preferably, both of these signals being are transmitted via the dedicated buses. Thereafter, data is routed from, for instance, the target, to the BIU via a corresponding dedicated bus. The BIU then routes the data to the initiator via the common bus.

REFERENCES:
patent: 5499239 (1996-03-01), Munter
patent: 5561669 (1996-10-01), Lenney et al.
patent: 5630077 (1997-05-01), Krein et al.
patent: 5832245 (1998-11-01), Gulick
patent: 5848279 (1998-12-01), Wu et al.

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