Method and apparatus of column redundancy for non-volatile analo

Details Method and apparatus of column redundancy for non-volatile analo Method and apparatus of column redundancy for non-volatile analo

1998-01-09

1999-12-14

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, G11C 700

Patent

active

060026200

ABSTRACT:
This invention provides column redundancy circuits in a storage array, which circuits are used in a non-volatile memory chip to increase the production yield due to manufacturing defects. The invention includes a scheme to latch and transfer the redundancy information, a redundancy logic circuit, a redundancy column driver, an array architecture with column redundancy, a scheme to program and read the column redundancy memory cells, a scheme to multiplex the fuses, and circuits to use an out-of-bound address as a column redundancy enable/disable signal.

REFERENCES:
patent: 4538245 (1985-08-01), Smarandoiu et al.
patent: 4546454 (1985-10-01), Gupta et al.
patent: 4617651 (1986-10-01), Ip et al.
patent: 5220531 (1993-06-01), Blyth et al.
patent: 5528540 (1996-06-01), Shibata et al.
patent: 5642316 (1997-06-01), Tran et al.
patent: 5657279 (1997-08-01), Savignac et al.
patent: 5796664 (1998-08-01), Tsuruda et al.
"SST Data Book", Silicon Storage Technology, Inc., pp. 17.1-17.7 (May 1995) .

Affiliated with

Also associated with

Rating

Method and apparatus of column redundancy for non-volatile analo does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus of column redundancy for non-volatile analo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus of column redundancy for non-volatile analo will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-869642