Static information storage and retrieval – Read/write circuit
Patent
1997-11-21
1999-12-14
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
36518909, G11C 1300
Patent
active
060026146
ABSTRACT:
Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals are dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can thus be programmed without reading out its memory state during the programming process, with programming margins being assured by the dependence of the read reference signals on the programming reference signals. Both sets of reference signals may be generated by reference cells which track variations in the operating characteristics of the memory cell with changes in conditions, such as temperature and system voltages, to enhance the reliability of memory programming and readout.
REFERENCES:
patent: 3660819 (1972-05-01), Frohman-Bentchkowsky
patent: 3755721 (1973-08-01), Frohman-Bentchkowksky
patent: 3801965 (1974-04-01), Keller et al.
patent: 4004159 (1977-01-01), Rai et al.
patent: 4054864 (1977-10-01), Audaire et al.
patent: 4090258 (1978-05-01), Cricchi
patent: 4122541 (1978-10-01), Uchida
patent: 4139910 (1979-02-01), Anantha et al.
patent: 4149270 (1979-04-01), Cricchi et al.
patent: 4181980 (1980-01-01), McCoy
patent: 4192014 (1980-03-01), Craycraft
patent: 4272830 (1981-06-01), Moench
patent: 4287570 (1981-09-01), Stark
patent: 4300210 (1981-11-01), Chakravarti et al.
patent: 4306300 (1981-12-01), Terman et al.
patent: 4327424 (1982-04-01), Wu
patent: 4357685 (1982-11-01), Daniele et al.
patent: 4388702 (1983-06-01), Sheppard
patent: 4415992 (1983-11-01), Adlhoch
patent: 4417325 (1983-11-01), Harari
patent: 4448400 (1984-05-01), Harari
patent: 4449203 (1984-05-01), Adlhoch
patent: 4462088 (1984-07-01), Giuliani et al.
patent: 4495602 (1985-01-01), Sheppard
patent: 4503518 (1985-03-01), Iwahashi
patent: 4558241 (1985-12-01), Suzuki et al.
patent: 4578777 (1986-03-01), Fang et al.
patent: 4586163 (1986-04-01), Koike
patent: 4612629 (1986-09-01), Harari
patent: 4627027 (1986-12-01), Rai et al.
patent: 4653023 (1987-03-01), Suzuki et al.
patent: 4661929 (1987-04-01), Aoki et al.
patent: 4701884 (1987-10-01), Aoki et al.
patent: 4709350 (1987-11-01), Nakagome et al.
patent: 4733394 (1988-03-01), Giebel
patent: 4771404 (1988-09-01), Mano et al.
patent: 4799195 (1989-01-01), Iwahashi et al.
patent: 4809224 (1989-02-01), Suzuki et al.
patent: 4847808 (1989-07-01), Kobatake
patent: 4853892 (1989-08-01), Hori
patent: 4890259 (1989-12-01), Simko
patent: 4903236 (1990-02-01), Nakayama et al.
patent: 4914631 (1990-04-01), Johnson et al.
patent: 4964079 (1990-10-01), Devin
patent: 4989179 (1991-01-01), Simko
patent: 5014242 (1991-05-01), Akimoto et al.
patent: 5021999 (1991-06-01), Kohda et al.
patent: 5043940 (1991-08-01), Harari
patent: 5095344 (1992-03-01), Harari
patent: 5163021 (1992-11-01), Mehrotra et al.
patent: 5168465 (1992-12-01), Harari
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5198380 (1993-03-01), Harari
patent: 5200959 (1993-04-01), Gross et al.
patent: 5218569 (1993-06-01), Banks
patent: 5258958 (1993-11-01), Iwahashi et al.
patent: 5262984 (1993-11-01), Noguchi et al.
patent: 5268318 (1993-12-01), Harari
patent: 5268319 (1993-12-01), Harari
patent: 5268870 (1993-12-01), Harari
patent: 5272669 (1993-12-01), Samachisa et al.
patent: 5293560 (1994-03-01), Harari
patent: 5295255 (1994-03-01), Malecek et al.
patent: 5299165 (1994-03-01), Kimura et al.
patent: 5307304 (1994-04-01), Saito et al.
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5321655 (1994-06-01), Iwahashi et al.
patent: 5351210 (1994-09-01), Saito
patent: 5422842 (1995-06-01), Cernea et al.
patent: 5422845 (1995-06-01), Ong
patent: 5428621 (1995-06-01), Mehrotra et al.
patent: 5430859 (1995-07-01), Norman et al.
patent: 5432735 (1995-07-01), Parks et al.
patent: 5434825 (1995-07-01), Harari
patent: 5438546 (1995-08-01), Ishac et al.
patent: 5440505 (1995-08-01), Fazio et al.
patent: 5444656 (1995-08-01), Bauer et al.
patent: 5450363 (1995-09-01), Christopherson et al.
patent: 5457650 (1995-10-01), Sugiura et al.
patent: 5469384 (1995-11-01), Lacey
patent: 5475693 (1995-12-01), Christopherson et al.
patent: 5485422 (1996-01-01), Bauer et al.
patent: 5487033 (1996-01-01), Keeney et al.
patent: 5495442 (1996-02-01), Cernea et al.
patent: 5497119 (1996-03-01), Tedrow et al.
patent: 5497354 (1996-03-01), Sweha et al.
patent: 5506813 (1996-04-01), Mochizuki et al.
patent: 5508958 (1996-04-01), Fazio et al.
patent: 5515317 (1996-05-01), Wells et al.
patent: 5523972 (1996-06-01), Rashid et al.
patent: 5539690 (1996-07-01), Talreja et al.
patent: 5541886 (1996-07-01), Hasbun
patent: 5544118 (1996-08-01), Harari
patent: 5546042 (1996-08-01), Tedrow et al.
patent: 5550772 (1996-08-01), Gill
patent: 5553020 (1996-09-01), Keeney et al.
patent: 5554553 (1996-09-01), Harari
patent: 5563828 (1996-10-01), Hasbun et al.
patent: 5566125 (1996-10-01), Fazio et al.
patent: 5568439 (1996-10-01), Harari
patent: 5574879 (1996-11-01), Wells et al.
patent: 5583812 (1996-12-01), Harari
patent: 5594691 (1997-01-01), Bashir
patent: 5596527 (1997-01-01), Tomioka et al.
patent: 5642312 (1997-06-01), Harari
patent: 5657332 (1997-08-01), Auclair et al.
patent: 5659550 (1997-08-01), Mehrotra et al.
patent: 5671388 (1997-09-01), Hasbun
patent: 5712180 (1998-01-01), Guterman et al.
patent: 5712819 (1998-01-01), Harari
patent: 5748546 (1998-05-01), Bauer et al.
patent: 5754566 (1998-05-01), Christopherson et al.
patent: 5776810 (1998-07-01), Guterman et al.
patent: 5781472 (1998-07-01), Sweha et al.
patent: 5796667 (1998-08-01), Sweha et al.
patent: 5801991 (1998-09-01), Keeney et al.
patent: 5802553 (1998-09-01), Robinson et al.
patent: 5806070 (1998-09-01), Norman et al.
Aritome, Seiichi, et al. "A Novel Side-Wall Transfer-Transistor Cell (SWATT Cell) For Multi-Level NAND EEPROMs." 1995 Technical Digest--International Electron Devices Meeting. (1995) : 275-278.
Bauer, M., et al. "TA 7.7: A Multilevel-Cell 32Mb Flash Memory." 1995 IEEE International Solid-State Circuits Conference, 1995 Digest of Technical Papers. (1995) : 132-133.
Hemink, G.J., et al. "Fast and Accurate Programming Method for Multi-level NAND EEPROMs." 1995 Symposium on VLSI Technology Digest of Technical Papers. (1995) : 129-130.
Bleiker, Christoph, and Melchior, Hans. "A Four-State EEPROM Using Floating-Gate Memory Cells." IEEE Journal of Solid-State Circuits, vol. SC-22, No. 3. (Jun. 1987) : 460-463.
Intel Corporation. "2764A Advanced 64K (8K.times.8) Production and UV Erasable PROMs." Memory Components Handbook. (Oct. 1985) : 4.10-4.20.
Chi, Min-hwa, and Bergemont, Albert. "Multi-level Flash/EPROM Memories: New Self-convergent Programming Methods for Low-voltage Applications," 1995 Technical Digest--International Electron Devices Meeting. (1995) : 271-274.
De Graaf, C., et al. "Feasibility of Multilevel Storage in Flash EEPROM Cells." Proceedings of the 25.sup.th European Solid State Device Research Conference. (Sep. 1995) : 213-216.
Aritome, Seiichi, et al. "A Side-Wall Transfer-Transistor Cell (SWATT Cell) for Highly Reliable Multi-Level NAND EEPROM's." IEEE Transactions on Electron Devices, vol. 44, No. 1. (Jan. 1997) : 145-152.
Gotou, H. "An Experimental Confirmation of Automatic Threshold Voltage Convergence in a Flash Memory Using Alternating Word-Line Voltage Pulses." IEEE Electron Device Letters, vol. 18, No. 10. (Oct. 1997) : 503-505.
Kim, H.S., et al. "Fast Parallel Programming of Multi-Level NAND Flash Memory Cells Using the Booster-Line Technology." 1997 Symposium on VLSI Technology Digest of Technical Papers. (1997) : 65-66.
Takeuchi, Ken, et al. "A Multi-Page Cell Architecture for High-Speed Programming Multi-Level NAND Flash Memories." 1997 Symposium on VLSI Circuits Digest of Technical Papers. (1997) : 67-68.
Choi, Jung Dal, et al. "A Triple Polysilicon Stacked Flash Memory Cell with Wordline Self-Boosting Programming." 1997 IEEE International Electron Devices Meeting. (1997) : 283-286.
Shen, Shih-Jye, et al. "Novel Self-Convergent Programming Scheme for Multi-Level P-Channel Flash Memory." 1997 IEEE International El
BTG International Inc.
Fears Terrell W.
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