Logic speed-up by selecting true/false combinations with the slo

Details Logic speed-up by selecting true/false combinations with the slo Logic speed-up by selecting true/false combinations with the slo

1996-06-17

1999-01-05

Santamauro, Jon

Electronic digital logic circuitry

Accelerating switching

326 93, 327407, H03K 1901

Patent

active

058567461

ABSTRACT:
A "slow" signal is not sent across chip to be combined with combinatorial logic, but rather, the logic with which it would be combined is partitioned such that there are two outputs, one if the "slow" signal would be true and a second if the "slow" signal would be false. Both of these outputs are then provided to a multiplexer. The original "slow" signal selects the correct signal, thus saving the interconnect time delay. The concepts also apply to combinations of multiple "slow" signals.

REFERENCES:
patent: 4940908 (1990-07-01), Tran
patent: 4970507 (1990-11-01), Cooperman et al.
patent: 5250855 (1993-10-01), Asato
patent: 5592103 (1997-01-01), Sutherland
patent: 5638290 (1997-06-01), Ginetti et al.
patent: 5644499 (1997-07-01), Ishii
patent: 5654898 (1997-08-01), Roetcisoender et al.

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