Method and circuit for calculating metrics for an analog viterbi

Details Method and circuit for calculating metrics for an analog viterbi Method and circuit for calculating metrics for an analog viterbi

1996-12-02

1999-08-03

Pham, Chi H.

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

375262, 371 438, H03D 100, H04L 2706

Patent

active

059334630

ABSTRACT:
A method and circuit for generating an updated metric signal for an analog Viterbi detector is disclosed. A circuit in accordance with the invention comprises a first summing amplifier 11 for subtracting a first reference voltage from a data signal; a second summing amplifier 12 for subtracting a second reference voltage from the data signal; a first comparator 21 for comparing the output of the first summing amplifier with a previous metric signal; a second comparator 22 for comparing the output of the second summing amplifier with the previous metric signal; a first AND gate 41 for combining the output of the first comparator and a first clock signal; a second AND gate 42 for combining the output of the second comparator and the first clock signal; a first sample-and-hold device 51 for sampling the output of the first summing amplifier 11 in response to the output of the first AND gate 41; and a second sample-and-hold device 52 for sampling the output of the second summing amplifier 12 in response to the output of the second AND gate 42. The updated metric signal is output on node 70. A holding capacitor 60 retains a charge associated with the updated metric signal during clock cycles when sample-and-hold circuits 51 and 52 are not triggered.

REFERENCES:
patent: 5373400 (1994-12-01), Kovacs
patent: 5384560 (1995-01-01), Yamasaki
patent: 5430768 (1995-07-01), Minuhin et al.
patent: 5469462 (1995-11-01), Kahlman et al.
patent: 5648949 (1997-07-01), Miyamoto et al.
patent: 5734680 (1998-03-01), Moore et al.
patent: 5774286 (1998-06-01), Shimoda

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