Static information storage and retrieval – Read/write circuit – For complementary information
Patent
1982-09-02
1985-06-04
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
For complementary information
365154, G11C 700
Patent
active
045218730
ABSTRACT:
A method of and a circuit arrangement for reading an integrated MTL(I.sup.2 L) store are described, wherein prior to or during a read operation, line capacities are discharged and in addition to the word line drivers and the bit line drivers, a read/write circuit is provided. Simultaneously with the selection of a word line (WL) or with a slight time delay (t1), two identical current sources (IRD0) are connected by means of two switches (S0 and S1) to the relevant bit lines (B0 and B1). As a result, the two injectors of the two bit line PNP transistors (T1 and T4) are supplied with the same currents. In a second phase (t2), the current sources (IRD0) are switched off so that the duration of the second time phase (t2) considerably exceeds the storage time constant (.tau.e) of the bit line PNP transistor (T4) connected to the switched "OFF" NPN transistor (T3) of a cell. The effective storage time constant (.tau.SAT) of the bit line PNP transistor (T1 ), connected to the switched on NPN cell transistor (T2), considerably exceeds the storage time constant (.tau.e). As a result of the different time constants (.tau.e and .tau.SAT), the two storage charges (Q1 and Q4) are discharged at different rates during the third phase (t3), thus generating a very fast and high output signal (.DELTA.VBL=VS).
REFERENCES:
patent: 4259730 (1981-03-01), Heuber et al.
patent: 4397002 (1983-08-01), Brosch et al.
K. Heuber et al., "Read/Write Circuitry", IBM Tech. Disclosure Bulletin, vol. 22, No. 9, Feb. 1980, pp. 4104-4105.
Heuber Klaus
Wiedmann Siegfried K.
DeBruin Wesley
International Business Machines - Corporation
Popek Joseph A.
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