Method and apparatus for stress testing a semiconductor memory

Details Method and apparatus for stress testing a semiconductor memory Method and apparatus for stress testing a semiconductor memory

1998-09-02

1999-12-07

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

365205, 365214, G11C 700

Patent

active

059994673

ABSTRACT:
Circuitry stress tests a Dynamic Random Access Memory (DRAM) by connecting a sense amplifier of the DRAM to at least two pairs of complementary bitlines within the same sub-array of the DRAM through two pairs of isolation transistors activated at substantially the same time. The circuitry thus provides for the stress testing of memory cells associated with sense amplifiers connected to only one sub-array within a DRAM or other semiconductor memory. The apparatus also provides an alternative to conventional methods for stress testing memory cells associated with sense amplifiers connected to more than one sub-array within a DRAM or other semiconductor memory.

REFERENCES:
patent: Re34718 (1994-09-01), Tobita
patent: 5298433 (1994-03-01), Furuyama
patent: 5339273 (1994-08-01), Taguchi
patent: 5367492 (1994-11-01), Kawaoto et al.
patent: 5469393 (1995-11-01), Thomann
patent: 5544108 (1996-08-01), Thomann
patent: 5726939 (1998-03-01), Cho et al.

Affiliated with

Also associated with

Rating

Method and apparatus for stress testing a semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for stress testing a semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for stress testing a semiconductor memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-831725