Static information storage and retrieval – Read/write circuit
Patent
1998-10-30
1999-12-07
Phan, Trong
Static information storage and retrieval
Read/write circuit
36518905, 36523008, G11C 1604, G11C 800
Patent
active
059994576
ABSTRACT:
A semiconductor integrated circuit incorporating DRAM 2 and a logic circuit 3 includes a vector generating circuit 40 formed on the common substrate. Upon a burn-in process, the vector generating circuit 40 and a refresh counter and control circuit 23 are activated to generate addresses, commands and data required for activating DRAM 2. In this manner, DRAM 2 and the logic circuit 3 can be activated independently, simultaneously, and the time required for the burn-in process can be reduced.
REFERENCES:
patent: 4855958 (1989-08-01), Ikeda
patent: 5698876 (1997-12-01), Yabe et al.
patent: 5854763 (1998-12-01), Gillingham et al.
Yabe, et al., "A Configurable DRAM Macro Design for 2112 Derivative Organizations to be Synthesized Using a Memory Generator," 1998 IEEE International Solid-State Circuits Conference, pp. 72-73.
Kabushiki Kaisha Toshiba
Phan Trong
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