Lateral high-voltage DMOS transistor with drain zone charge drai

Details Lateral high-voltage DMOS transistor with drain zone charge drai Lateral high-voltage DMOS transistor with drain zone charge drai

1996-07-16

1999-03-16

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257409, 257492, 257493, H01L 2976, H01L 2994, H01L 2358

Patent

active

058834133

ABSTRACT:
In many circuits in which a current is switched off, a high voltage appears at the drain electrode of a transistor, in particular in the case of an inductive load. When a lateral high-voltage DMOST is used, such a high voltage may lead to instability in the transistor characteristics or may even damage the transistor. To avoid this problem, the drain of a high-voltage LDMOST is locally provided with a strongly doped n-type zone 18, 21 (in the case of an n-channel transistor) which extends, seen from the surface, down into the semiconductor body to a greater depth than does the source zone 8, so that a pn-junction is formed at a comparatively great depth in the semiconductor body having a breakdown voltage that is lower than the BV.sub.ds of the transistor without this zone. The energy stored in the inductance may thus be drained off through breakdown of the pn-junction. This breakdown is separated from the normal current path of the transistor owing to the comparatively great depth of the pn-junction, so that the robustness of the transistor is improved. This deep zone in the drain may be formed, for example, by a buried layer at the boundary between an epitaxial layer and the substrate.

REFERENCES:
patent: 4300150 (1981-11-01), Colak
patent: 4989058 (1991-01-01), Colak et al.
patent: 5635742 (1997-06-01), Hosi et al.

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