Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1997-08-26
1998-10-06
Wallace, Valencia
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257 67, 257 69, 257379, 257903, 365154, H01L 2702
Patent
active
058180907
ABSTRACT:
A semiconductor device having an integrated circuit with high density load elements in memory cells forming a memory array wherein the load elements are either of the active (e.g., TFTs) or passive (e.g., resistance) type and designed so that the connection path between these elements and active element domains is extended to be longer within the same or smaller scale of the memory cell configuration. For this purpose, the connection path may be made to meander to provide for greater length, i.e., extend in one direction and then another within a single memory cell configuration. This further creates additional space for extending the resistance value of the active or passive load element which, in turn, permits a reduction in drain current, i.e., current consumption, during operational conditions of the memory cells or other circuits. The design further provides for improved mask alignment accuracy since the load element is completely constructed within a planar extent of the memory cell so that predetermined lengths of the element and predetermined, desired resistance levels can be achieved and maintained without concern for resistance level changes due to subsequent integrated circuit processing and contaminate migration.
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Yamanaka et al., "A 25 .mu.m.sup.2, New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity," IEDM 1988, pp. 48-51.
Seiko Epson Corporation
Wallace Valencia
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