Process for manufacturing LDD CMOS devices

Details Process for manufacturing LDD CMOS devices Process for manufacturing LDD CMOS devices

1987-09-18

1988-09-13

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 34, 437 44, 437 57, 437 27, 357 233, 357 2311, 357 42, H01L 21265, H01L 2700

Patent

active

047710144

ABSTRACT:
A method for making a CMOS integrated circuit device saves on masking steps by using unmasked blanket implantations at various steps of the process, such as setting the threshold voltages of the transistors, forming a lightly doped drain for the N-channel transistor, and for forming the source/drain regions of the N-type transistor.

REFERENCES:
patent: 4530150 (1985-07-01), Shirato
patent: 4562638 (1986-01-01), Schwabe et al.
patent: 4590663 (1986-05-01), Haken
patent: 4599789 (1986-07-01), Gasner
patent: 4637124 (1987-01-01), Okuyama et al.
patent: 4642878 (1987-02-01), Maeda
Ogura et al., "A Half-Micron MOSFET Using Double Implanted LDD", IEDM 1982, pp. 718-721.

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