Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1993-04-12
1994-03-29
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Bad bit
365 96, 365201, 36523003, G11C 1300
Patent
active
052991601
ABSTRACT:
An input/output switching circuit is provided between I/O blocks and I/O pads. The input/output switching circuit includes fusable elements connected in series, and a switching elements for defining connection path of I/O blocks and I/O pads in response to a potential of each one end of the fusable elements. The switching element connects an I/O block to an I/O pad in a one-to-one correspondence when all the fusable elements are conductive. When one fusable element is disconnected, the switching element isolates a corresponding defective I/O block from an I/O pad, and switches the connection path of each I/O block towards the pad corresponding to the defective I/O block. In a semiconductor memory device having an error checking bit, the manufacturing yield of a semiconductor memory device can be improved by isolating a defective I/O block that cannot be repaired by a normal redundant circuit scheme, and operating the same as a semiconductor memory device without an error checking bit.
REFERENCES:
A. Ohta et al., "A 7-ns 1-Mo BiCMOS ECL SRAM with Shift Redundancy", IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991.
Fears Terrell W.
Mitsubishi Denki & Kabushiki Kaisha
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