Semiconductor memory device having on-chip test circuit

Details Semiconductor memory device having on-chip test circuit Semiconductor memory device having on-chip test circuit

1990-06-05

1992-02-11

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

36518901, G11C 1300

Patent

active

050880632

ABSTRACT:
In a memory cell array of a semiconductor memory device, a plurality of detection circuits (14, 15, 20) are provided in correspondence with a plurality of columns. An output line (L) is provided in common to the detection circuits (14, 15, 20). The output line (L) is provided with plural junction points (nl to nn) to which detection results from the detection circuits (14, 15, 20) are separately applied. Dividing transistors (Tl to Tn) are provided between the junction points (nl to nn). During testing, the work lines (WLl to WLn) are selected sequentially. Test results for the memory cells (MC1 to MC4 ) connected to the selected word line are outputted at the corresponding junction points (nl to nn), respectively. Simultaneously, a dividing transistor corresponding to the selected word line is rendered non-conductive, the remaining dividing transistors being rendered conductive. As a result, the output line (L) is divided into two parts at a portion of the non-conductive transistor. Detection results outputted to the respective divided parts of the output line (L) are monitored and a portion at which a detection result is changed in each divided part is found out.

REFERENCES:
Matsumura, "On-Chip Parallel Testing Technology for VLSI Memories", Technology for Improving Testing Efficiency Suitable for Large Capacity Memories, NTT Communications Laboratories, p. 165.
Inoue et al., "Parallel Testing Technology for VLSI Memories", 1987 International Test Conference, p. 45.1, pp. 1066-1071.

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