Predecoding and steering mechanism for instructions in a supersc

Details Predecoding and steering mechanism for instructions in a supersc Predecoding and steering mechanism for instructions in a supersc

1994-02-14

1999-10-26

Vu, Viet D.

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

712213, G06F 938

Patent

active

059745347

ABSTRACT:
A computing system includes a main memory, an instruction cache and a processor. The processor includes memory interface means, predecoding means, interface means, a first arithmetic logic unit, a second arithmetic logic unit and steering means. The memory interface means is connected to the main memory and fetches instructions from the main memory. The predecoding means is connected to the memory interface means and predecodes the instructions to generate predecode bits. The predecode bits indicate whether and how the instructions may be bundled. The interface means is connected to the predecoding means and the instruction cache. The interface means stores the instructions and the predecode bits in the instruction cache and fetches the instructions from the instruction cache with the predecode bits. The steering means is connected to the interface means, the first arithmetic logic unit and the second arithmetic logic unit. The steering means steers each of the instructions to one of the first integer arithmetic logic unit and the second integer arithmetic logic unit for execution. The steering means utilizing the predecode bits to steer the instructions.

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