SRAM having P-channel TFT as load element with less series-conne

Details SRAM having P-channel TFT as load element with less series-conne SRAM having P-channel TFT as load element with less series-conne

1997-03-11

1999-10-26

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257903, 438153, 438154, 438199, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

059733691

ABSTRACT:
A memory cell for a semiconductor device includes two pairs of a transfer transistor and a drive transistor at a first level and a pair of load transistors above the two pairs of transfer and drive transistors at a second level. Each of the load transistors includes a gate, a source/drain, and a channel. The cell further includes a pair of contacts extending between the first and second levels and that connect one of the gates to a respective one of the two pairs of transfer and drive transistors. Each load transistor gate includes a portion that overlies its respective channel and a lateral extension therefrom that contacts a respective one of the contacts. The extension of one load transistor gate overlaps the source/drain of the other load transistor adjacent the respective one of the contacts.

REFERENCES:
patent: 5198683 (1993-03-01), Sivan
patent: 5404030 (1995-04-01), Kim et al.
patent: 5475240 (1995-12-01), Sakamoto
patent: 5594267 (1997-01-01), Ema et al.
K. Tsutumi et al., "A High-Performance SRAM Memory Cell with LDD-TFT Loads", 1991 Symposium on VLSI Technology Digest of Technical Papers, pp. 23 and 24.
K. Itabashi et al., "A Split Wordline Cell for 16Mb SRAM Using Polysilicon Sidewall Contacts", 1991 IEEE, pp. 477-479.
H. Ohkubo et al., "16 Mbit SRAM Cell Technologies for 2.0V Operation", 1991 IEEE, pp. 481-484.

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