Prevention of die loss to chemical mechanical polishing

Details Prevention of die loss to chemical mechanical polishing Prevention of die loss to chemical mechanical polishing

1998-05-29

1999-10-26

Utech, Benjamin

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438692, 438691, 438706, 438712, 216 84, H01L 2100

Patent

active

059727985

ABSTRACT:
Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

REFERENCES:
patent: 5271798 (1993-12-01), Sandhu et al.
patent: 5362669 (1994-11-01), Boyd et al.
patent: 5401691 (1995-03-01), Caldwell
patent: 5503962 (1996-04-01), Caldwell
patent: 5627110 (1997-05-01), Lee et al.
patent: 5705320 (1998-01-01), Hsu et al.
patent: 5795825 (1998-08-01), Sugano

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