High quality isolation for high density and high performance int

Details High quality isolation for high density and high performance int High quality isolation for high density and high performance int

1997-06-05

1999-10-26

Fourson, George

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438445, 438438, 438696, H01L 21762

Patent

active

059727730

ABSTRACT:
A novel semiconductor fabrication process having the advantages of conventional LOCOS (process simplicity and reduced defects) while providing a scaleable, planar isolation region between active regions formed in a semiconductor substrate. The preferred process includes formation of a barrier layer and a masking layer over the substrate. An active region mask defines an exposure region of the masking layer. The exposure region is etched to form an opening, exposing a portion of barrier layer in the opening. A spacer is added inside the opening, around a perimeter of the opening to define a second exposure region. The barrier layer, and substrate, under the second exposure region, but not under the spacer, are etched to form an isolation region opening. The isolation region opening may have a suitable isolating material, such as silicon oxide, grown, filled, or some combination of both, in the isolation region opening. The spacer width and the depth of the isolation region opening are independently controllable.

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