Semiconductor memory device with built-in test circuit and metho

Details Semiconductor memory device with built-in test circuit and metho Semiconductor memory device with built-in test circuit and metho

1990-07-03

1992-09-15

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

371 211, G11C 1300

Patent

active

051483980

ABSTRACT:
A semiconductor memory device having a test mode function and a plurality of memory blocks each having memory cells arranged in a matrix and a method for testing the device. The device includes a unit for writing identical data in each memory cell of the plurality of memory blocks, a unit for simultaneously reading data of one bit from each of the plurality of memory blocks, a unit for detecting coincidence or non-coincidence of the read bits and outputting a result of the detection, and a unit for sequentially outputting the read bits one by one when the result is the non-coincidence. As a result, an address of a "failing" bit can be detected to facilitate a failure analysis, thereby reducing test time.

REFERENCES:
patent: 4464750 (1984-08-01), Tatematsu
patent: 4899313 (1990-02-01), Kumanoya et al.
patent: 4916700 (1990-04-01), Ito et al.
IBM Technical Disclosure Bulletin, vol. 30, No. 11, Apr. 1988, N.Y., "Repair Calculation For Randon-Access Memory Redundance Using Built-in Logic and Scannable Latches", pp. 424-425.
IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb. 1989, N.Y., "A redundancy Test-Time Reduction Technique in 1-Mbits DRAM With a Multibit Test Mode", Y, Nishimura et al., pp. 43-49.

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