Bit phase synchronizing method and bit phase synchronizing circu

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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Details

327152, 327153, 327161, 327163, 327251, 327253, 327538, H04L 702

Patent

active

060410892

ABSTRACT:
(1) A bit phase adjusting circuit receives input data Din and passes it to a first group of delay gates which are connected in series to generate a set of data available for selection, the set including the input data Din and the input Din delayed by different amounts. The bit phase adjusting circuit selects one of the data from this set and outputs it to a bit change detecting circuit having a second group of delay gates which are connected in series. (2) In the bit change detecting circuit, at a time controlled by a reference clock signal, it is judged whether or not the input and the output data of a pth-stage delay gate of the second delay gate group coincide with each other and whether or not the output data of the pth-stage delay gate and a (p+1)th-stage delay gate coincide with each other. A change point detecting signal is generated which shows whether or not a change point of the output data from the pth-stage delay gate is within a specified range before and after the judgement time. (3) The input data is synchronized in phase with the reference clock signal by changing the data that is selected by the bit phase adjusting circuit according to the change point detecting signal. Stable bit phase synchronization is achieved by a bit phase synchronizing method including the processes (1) to (3). The delay gates of at least the first group are controlled so that the respective delay quantities or duration of the delay gates can be kept constant.

REFERENCES:
patent: 4940910 (1990-07-01), Jiang
patent: 5621774 (1997-04-01), Ishibashi et al.
patent: 5654663 (1997-08-01), McClure et al.
patent: 5663668 (1997-09-01), Hayashi et al.

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