Semiconductor memory device and method of testing the same

Details Semiconductor memory device and method of testing the same Semiconductor memory device and method of testing the same

1998-11-20

2000-03-21

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

365200, G11C 700

Patent

active

060410027

ABSTRACT:
In a method of testing a leakage of a charge of DRAM memory cells, in test mode, test mode signal TM-BLLTC from test mode signal generating circuit is supplied to a partial row decoder and a column decoder, so that a selection of all the word lines is prohibited and all the columns of a memory cell array are selected. In this state, a write cycle is executed and data is supplied to each bit line from a data input and output line. Based on the data from the data input and output line, the voltages of the bit lines can be controlled directly, and a charge leakage test of the DRAM memory cells can be carried out accurately, without using data read from the memory cells.

REFERENCES:
patent: 5629943 (1997-05-01), McClure
patent: 5666317 (1997-09-01), Tanida et al.
patent: 5796671 (1998-08-01), Wahlstrom
Toshiaki Kirihata et al.; "Flexible Test Mode Approach for 256-Mb DRAM"; IEEE Journal of Solidstate Circuits, Oct. 1997, vol. 32 No. 10, pp. 1525-1533.

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