Static information storage and retrieval – Addressing – Multiple port access
Patent
1992-04-08
1994-01-25
LaRoche, Eugene R.
Static information storage and retrieval
Addressing
Multiple port access
36523002, 36523003, 36523006, G11C 800
Patent
active
052821773
ABSTRACT:
The specification discloses preferred circuits and methods for performing a block write in a video random access memory circuit (VRAM). The VRAM has a plurality of memory registers, an address bus, and a data bus. The VRAM also has a multiple write register circuit with a plurality of write registers. During write register load cycles, data is written from the data bus to individual write registers which are specified by addresses received on the address bus. During a block write cycle, data is written from an individual write register to a selected block of memory registers; the block having a predefined number of memory registers within a row. The block of memory registers is specified by memory register base address received on the address bus. The memory register base address is the address of the first memory register in the block of memory registers. An individual write register from which data is written to the block of memory registers is selected during a block write cycle by an address received on the data bus.
REFERENCES:
patent: 4566082 (1986-01-01), Anderson
patent: 4725945 (1988-02-01), Kronstadt et al.
patent: 4755971 (1988-06-01), Jasmer et al.
patent: 4933910 (1990-06-01), Olson et al.
patent: 5047989 (1991-09-01), Canepa et al.
patent: 5060145 (1991-10-01), Scheuneman et al.
patent: 5134583 (1992-07-01), Matsuo et al.
patent: 5148523 (1992-09-01), Harlin et al.
Micron Technology, Inc., Product Brochure, "Multiport Dynamic RAM," 1990.
Micron Technology, Inc., Product News, "1MEG Video RAM--Description & Function," 1989.
Jeff Mailloux, et al., "Designing Solutions With Multiport DRAMs," Electronic Engineering International, Oct., 1991.
Micron Technology, Inc., Brochure, "Triple Port DRAM--256K.times.4 DRAM With Dual 512.times.4 SAMs", 1991.
Jeff Mailloux, et al., "Speed Memory, Ease Timing Requirements With VRAM Functions," Nov. 23, 1989, Electronic Design.
LaRoche Eugene R.
Micro)n Technology, Inc.
Nguyen Tan
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