Semiconductor memory device of divided word line

Details Semiconductor memory device of divided word line Semiconductor memory device of divided word line

1991-05-24

1994-01-25

Heyman, John S.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365204, 307449, G11C 11407

Patent

active

052821757

ABSTRACT:
In a SRAM of a selected word line structure, each local decoder is connected to a corresponding main word line and a corresponding Z decoder signal line. Each local decoder includes a circuit including two MOS transistors connected in series to each other which circuit has one end grounded. The corresponding local word line is connected to a node between these two transistors. Out of the corresponding main word line and the corresponding Z decoder signal line, one is connected to the gates of these transistors and the other is connected to the other end of said circuit, which the other end is not grounded. The potential on the corresponding local word line attains a high level only when the potential on the signal line connected to the gate of these two transistors, is at a logical level at which the transistor can be turned on and the potential on said one signal line is at a high level. Theoretically, therefore, each local word line is controlled to be activated or inactivated by the operations of two elements in the corresponding local decoder.

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Aizaki et al., "A 15 ns 4 Mb CSMO SRAM", IEEE ISSCC Digest of Technical Papers, Thursday, Feb. 15, 1990, pp. 126-127.
Tran et al., "An 8 ns BiCMOS 1 Mb ECL SRAM with a Configurable Memory Array Size", IEEE ISSCC Digest of Technical Papers, Wednesday, Feb. 15, 1989, pp. 36-37.
Kohno et al., "A 14-ns 1-Mbit CMOS SRAM with Variable Bit Organization", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1060-1066.

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