Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-06-03
1998-01-20
Tsai, Jey
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438638, 438583, 438238, 148DIG20, H01L 214763
Patent
active
057100780
ABSTRACT:
A method for reducing the contact resistance of an overlying metal bit line structure, to underlying polycide gate structure, has been developed. A borderless, or non-fully landed contact hole, is opened in an insulator layer, to expose the top surface of the underlying polycide gate structure. The anisotropic, dry etching of the insulator is then continued, resulting in the exposure of a portion of the sides of the polycide gate structure. A subsequent bit line metal structure, now contacts both the top surface, as well as a portion of the sides, of the polycide gate structure, resulting in a contact resistance reduction, due to the increased contact area.
REFERENCES:
patent: 5399235 (1995-03-01), Mutsaers et al.
patent: 5457070 (1995-10-01), Hirade
patent: 5476814 (1995-12-01), Ohshima et al.
patent: 5576243 (1996-11-01), Wuu et al.
H.W. Chung et al. "Evaluations of Borderless Vias for Sub-Half Micron Technologies", Pub Jun. 27-29, 1995, VMIC Conference, pp. 667-669.
Ackerman Stephen B.
Saile George O.
Tsai Jey
Vanguard International Semiconductor Corporation
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