Column select line enable circuit for a semiconductor memory dev

Details Column select line enable circuit for a semiconductor memory dev Column select line enable circuit for a semiconductor memory dev

1997-11-24

1999-09-28

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

365194, 36518906, G11C 800

Patent

active

059599367

ABSTRACT:
A column select line enable circuit prevents the first bit in a sequence of output data from being missed, thereby reducing tRCD in a synchronous memory device. The circuit delays a predetermined period of time after a row active command is applied to the memory device and then activates a column select enable line regardless of the state of the system clock signal. The column select enable line is maintained in an active state for a second period of time to allow the first bit of data to be read from the device. Thereafter, the column select enable line is enabled and disabled responsive to the system clock signal to read the remaining bits in the sequence of output data in a conventional manner. In a preferred embodiment, the circuit does not enable the column select enable line unless a decoded bank address signal is active.

REFERENCES:
patent: 5031150 (1991-07-01), Ohsawa
patent: 5414672 (1995-05-01), Ozeke et al.
patent: 5703828 (1997-12-01), Park et al.

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