Method and apparatus for detecting errors in the writing of data

Details Method and apparatus for detecting errors in the writing of data Method and apparatus for detecting errors in the writing of data

1998-08-17

1999-09-28

Nelms, David

Static information storage and retrieval

Addressing

Multiple port access

36518901, 365221, 36518905, G11C 800

Patent

active

059599324

ABSTRACT:
A buffer memory includes at least one memory including a plurality of memory locations, and at least one write-control circuit. When data is written to one of the plurality of memory locations, the at least one write-control circuit causes at least one bit of validation information to be written to the at least one memory to indicate that the data written to the one of the plurality of memory locations is valid. In response to data being read from the one of the plurality of memory locations, the at least one write-control circuit causes the at least one bit of validation information to be overwritten to indicate that the data stored in the one of the plurality of memory locations is invalid. In another embodiment, a method for operating a buffer memory including a plurality of memory locations includes steps of: (a) when data is written to one of the plurality of memory locations, storing at least one bit of validation information in the buffer memory indicating that the data written to the one of the plurality of memory locations is valid; and (b) in response to the data being read from the one of the plurality of memory locations, overwriting the at least one bit of validation information to indicate that the data stored in the one of the plurality of memory locations is invalid.

REFERENCES:
patent: 5088061 (1992-02-01), Golnabi et al.
patent: 5568443 (1996-10-01), Dixon et al.
patent: 5751887 (1998-05-01), Nitta et al.
patent: 5771331 (1998-06-01), Aoki et al.

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