DRAM incorporating self refresh control circuit and system LSI i

Details DRAM incorporating self refresh control circuit and system LSI i DRAM incorporating self refresh control circuit and system LSI i

1998-11-03

1999-09-28

Phan, Trong

Static information storage and retrieval

Read/write circuit

Data refresh

36518905, 36523006, 36523008, 365236, G11C 700

Patent

active

059599251

ABSTRACT:
A DRAM and a system LSI incorporating the DRAM. The DRAM has a self refresh address control section (11) inputs a control signal to optionally specify a period of a self refresh operation for the DRAM, a self refresh control circuit (7,71) for specifying the period of an address signal to be used for the self refresh operation and for outputting a self cycle signal, and a row address buffer (8) for providing addresses to the memory cell array (10) based on the self cycle signal as a trigger signal.

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patent: 5502677 (1996-03-01), Takahashi
patent: 5532968 (1996-07-01), Lee
patent: 5818777 (1998-10-01), Seyyedy

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