Dynamic memory apparatus having a sense amplifier and a referenc

Static information storage and retrieval – Read/write circuit – Differential sensing

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365149, G11C 1124

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active

046690654

ABSTRACT:
A memory apparatus has a dummy cell comprising two sets of series connections of MOS transistors and capacitors, respectively, connected to a pair of bit lines, which are connected to a sense amplifier of a flip-flop type, and a third MOS transistor having a source and a drain thereof connected between junction points of the MOS transistors and the capacitors of the dummy cell. The capacitors are charged at a high level potential and a low level potential, respectively, of the bit lines and then they are shorted to each other through the third MOS transistor so that they have a common potential of a middle potential level. The potential of the middle level can be supplied to a pair of input terminals to the flip-flop type sense amplifier as a reference potential signal. Thus, it is possible to assure a stable sensing operation by the sense amplifier which is free from an influence of a change in the potential of a substrate of the memory apparatus.

REFERENCES:
patent: 4099265 (1978-07-01), Abe
patent: 4578780 (1986-03-01), Baba
patent: 4581719 (1986-04-01), Penchuk

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