Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1999-03-31
1999-09-28
Codd, Bernard
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
438633, 438638, 438639, 438669, 438692, 438723, 438737, 438743, 438763, 438778, 438975, 430 22, 430314, 430317, 430318, 216 38, 216 39, 216 75, 216 80, 216 89, C03C 1502, G03F 900, G03C 500
Patent
active
059588004
ABSTRACT:
A method of removing a planarized insulating layer from over an alignment mark on a wafer. The invention allows steppers to see alignment marks without the difficulty of viewing the alignment marks through the insulating layer overlying the alignment marks. The method begins by chemical mechanical polishing a conformal oxide layer over a substrate. Next, a first photoresist layer is formed over the conformal oxide layer. Then vias are etched in the conformal oxide layer in the device area and etch the conformal oxide layer in the alignment mark area. Subsequently, we form a second photoresist layer over the first photoresist layer and the conformal oxide layer. The second photoresist layer filling the vias, but not the alignment mark resist opening. Then etch the second photoresist layer leaving sidewall spacers on the sidewall of the first photoresist layer in the alignment mark area and leaving photoresist plugs filling the vias. Next, anisotropically etch the conformal oxide layer in the alignment mark area exposing the alignment mark patterns. Then, a metal layer is formed over the surface. The metal layer is patterned.
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Jang Syun-Ming
Yu Chen-Hua
Ackerman Stephen B.
Codd Bernard
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company , Ltd.
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