Semiconductor memory device with redundant cells

Details Semiconductor memory device with redundant cells Semiconductor memory device with redundant cells

1982-12-27

1986-07-29

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Bad bit

G11C 700

Patent

active

046034048

ABSTRACT:
A semiconductor memory device in which the memory cells are arranged in matrix form and in which, when a defective cell exists among the memory cells and a row or column containing the defective cell is selected, the selected row or column is switched to a predetermined redundant row or a predetermined redundant column additionally and independently provided. A plurality of switching circuits are provided, each of the switching circuits being connected to the output of the decoder circuit, which select the row or the column of memory cells. A fusing circuit is connected to each of the switching circuits, and when the fuse in the fusing circuit is disconnected, the row or the column containing the defective cell is switched to the redundant row or the redundant column.

REFERENCES:
patent: 3753244 (1973-08-01), Sumilas et al.
patent: 3755791 (1973-08-01), Arzubi
patent: 3940740 (1976-02-01), Coontz
patent: 4281398 (1981-07-01), McKenny et al.
patent: 4389715 (1983-06-01), Eaton, Jr. et al.

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