Semiconductor memory device having a stacked type capacitor and

Details Semiconductor memory device having a stacked type capacitor and Semiconductor memory device having a stacked type capacitor and

1992-07-24

1994-02-08

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257309, H01L 2968

Patent

active

052850927

ABSTRACT:
A capacitor of a semiconductor memory device includes a planar type capacitor portion formed on a surface of an impurity region and a stacked type capacitor portion extending above the gate electrode. The stacked capacitor portion has a three-layer structure of polycrystalline silicon in which upper, lower and side surfaces of a lower electrode are surrounded by a dielectric layer and the upper electrode. A portion of a dielectric layer in the stacked capacitor portion is coupled to another dielectric layer formed on the surface of one impurity region. The capacitor has a planar type capacitor provided in the planar area of occupation of the stacked capacitor portion, whereby the capacitance of the capacitor can be increased without increasing the planar area of occupation.

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T. Ema et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS," IEDM, 1988, pp. 592-595.
R. M. Geffkan et al., "Process for High-Capacitance Single-Device Memory Cell", IBM Technical Disclosure Bulletin, vol. 21, No. 6, Nov. 1978, pp. 2257-2259.

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