System having a receive data register for storing at least nine

Details System having a receive data register for storing at least nine System having a receive data register for storing at least nine

1997-08-29

1999-09-28

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

710 9, 710 14, 710 30, 709221, 709234, 711156, G06F 1328, G06F 1342

Patent

active

059580240

ABSTRACT:
An asynchronous serial port having a control register and at least one data register exchanges data with a serial bus. The asynchronous serial port includes an indicator representing whether the data register contains all of the data bits, or whether some of the data may be stored in the control register. When a nine-bit data source (or any data source having more than eight bits of data) is received, the bits need not be divided among multiple registers, but can all be stored in the receive-data register. This is particularly useful during DMA or when the exchange of data has been suspended, for example by an interrupt, while additional frames may be received by the asynchronous serial port. Because frames are stored in a single register when an extended write bit or an extended read bit is set. Further, the receive data register also stores status bits associated with received data. This is especially useful during DMA operations, when status, including parity, frame, or overrun errors can be associated with a particular data item examining the stored DMA data itself.

REFERENCES:
patent: 4631666 (1986-12-01), Harris et al.
patent: 4698802 (1987-10-01), Goke et al.
patent: 4713748 (1987-12-01), Magar et al.
patent: 4785396 (1988-11-01), Murphy et al.
patent: 4823305 (1989-04-01), Holdren et al.
patent: 4885538 (1989-12-01), Hoenniger, III et al.
patent: 4972432 (1990-11-01), Wilson et al.
patent: 5150359 (1992-09-01), Wilson et al.
patent: 5166872 (1992-11-01), Weaver et al.
patent: 5535373 (1996-07-01), Olnowich
patent: 5548711 (1996-08-01), Brant et al.
patent: 5596724 (1997-01-01), Mullins et al.
patent: 5812820 (1998-09-01), Loram
Am186.TM.ED/EDLV Microcontrollers User's Manual, Advanced Micro Devices, Inc., 1997, pp. ii through 10-16.
Am186.TM.ED, High Performance, 80C186-and 80C188-Compatible, 16-Bit Embedded Microcontroller, Advanced Micro Devices, Inc., Mar. 1997, pp. 1, 2, 13, 47 and 48.
Am186.TM.ES and Am188.TM.ES User's Manual, Advanced Micro Devices, Inc., 1997, pp. i through ii, 9-1 through 9-14, and 10-1 through 10-14.
Am186.TM.ES/ESLV and Am188.TM.ES/ESLV, Advanced Micro Devices, Inc., Publication 20002, Rev. B, Amendment /0, Feb. 1997, pp. 1 through 12, pp. 25 through 52.

Affiliated with

Also associated with

Rating

System having a receive data register for storing at least nine does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System having a receive data register for storing at least nine , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System having a receive data register for storing at least nine will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-697669