SRAM memory cell design having complementary dual pass gates

Details SRAM memory cell design having complementary dual pass gates SRAM memory cell design having complementary dual pass gates

1996-12-12

1998-11-03

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Flip-flop

365154, 365190, 365181, 365161, 257903, 257904, 257 67, 257350, G11C 11412

Patent

active

058318976

ABSTRACT:
A memory cell in which data is written and read from a pass gate. The memory cell has a connection to a first pass gate, connecting the memory cell to a bit line. Additionally, the memory cell has a second pass gate connecting the memory cell to a complementary bit line. The pass gates are controlled by a word line and a complementary word line.

REFERENCES:
patent: 5040146 (1991-08-01), Mattausch et al.
patent: 5347487 (1994-09-01), Dao et al.
patent: 5353251 (1994-10-01), Uratani et al.
patent: 5623440 (1997-04-01), Saito

Affiliated with

Also associated with

Rating

SRAM memory cell design having complementary dual pass gates does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with SRAM memory cell design having complementary dual pass gates, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SRAM memory cell design having complementary dual pass gates will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-697492