Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-08-18
1998-09-29
Shah, Alpesh M.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711208, G06F 900
Patent
active
058157298
ABSTRACT:
A method for improving the load time of code and data descriptors is provided. The invention utilizes hardware validation logic for code and data descriptors, but uses a software program to validate system descriptors. In those instances where the descriptor being loaded is a code or data descriptor, system validation checks are not performed. This allows code and data descriptors to be validated during the write back stage of the descriptor store operation, thereby eliminating processing delays typically associated with performing validation. If the descriptor is found invalid by the hardware validation logic, a branch is made to a software program which is used to determine whether the descriptor is invalid, or is actually a system descriptor. If it is a system descriptor, then system descriptor validation checks are performed by a software program.
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Henry G. Glenn
Parks Terry
Huffman James W.
Integrated Device Technology Inc.
Shah Alpesh M.
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