Excavating
Patent
1996-11-12
1999-04-27
Beausoliel, Jr., Robert W.
Excavating
324765, G01R 3128
Patent
active
058987002
ABSTRACT:
A test signal generator and method for testing a semiconductor wafer having a plurality of memory chips. A plurality of input buffers buffer test timing signals applied through a plurality of input terminals to the memory chips in test mode. A direct current source supplies a direct current of a given level to each of the terminals. The direct current source comprises a MOS transistor for supplying the direct current including a fuse with a first node connected between the terminal and buffer and a second node for receiving the direct current. The fuse is cut by an electric or laser cutter after wafer testing is complete. This enables a probe card for performing the wafer testing to be fabricated with a reduced number of probe tips, thereby overcoming the limitation of a test driver and allowing the simultaneous testing of semiconductor wafers having a plurality of memory chips having different pad configurations.
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Beausoliel, Jr. Robert W.
Iqbal Nadeem
Samsung Electronics Co,. Ltd.
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